1. Field of the Invention
The present invention relates to an insulated gate semiconductor device having a trench gate, and more particularly, to an improvement for improving an RBSOA.
2. Description of the Prior Art
An insulated gate semiconductor device is a semiconductor device having a structure in which gate electrodes are faced with a semiconductor layer disposed for creating a channel through an insulation film. An insulated gate bipolar transistor (hereinafter “IGBT”) and a MOS transistor are typical examples of such an insulated gate semiconductor device. In a generally popular structure of an insulated gate semiconductor device, a number of unit cells which are connected parallel to each other are formed in a single semiconductor substrate, to obtain a large main current.
In particular, an insulated gate semiconductor device having a trench gate, that is, a device which is structured so that a gate electrode is buried in a trench which is formed in one major surface of a semiconductor base is attracting an attention as an excellent device which is advantageous in that it is possible to increase the integration degree of the device, since it is easy to miniturize the unit cells in such a device.
FIG. 29 is a cross sectional view of a conventional insulated gate bipolar transistor having a trench gate (hereinafter “trench IGBT”), which serves as the background of the present invention. In a conventional device 151, a p+ collector layer 1, an n+ buffer layer 2, and an n− semiconductor layer 3 are sequentially stacked in this order in a silicon semiconductor base which is formed as a flat plate. Within a cell region CR of the semiconductor base, a number of trenches 7 are formed parallel to each other with a certain distance Wcel from each other in a top major surface of the semiconductor base (i.e., a major surface in which the n− semi conductor layer 3 is formed).
Further, in the cell region CR, a p base layer 4 is formed in a surface portion of the n− semiconductor layer 3. Still further, in a surface portion of the p base layer 4, an n+ emitter layer 5 is selectively formed so as to be adjacent to side walls of the trenches 7. Gate insulation films 8 are formed on inner surfaces of the trenches 7, and a gate electrode (i.e., trench gate) 10 is buried inside the gate insulation films 8. A region of the p base layer 4 which is faced with the gate electrode 10 and is between the n+ emitter layer 5 and the n− semiconductor layer 3 functions as a channel region.
The cell region CR is surrounded by a gate wire region GR. In the gate wire region GR, a gate wire line GL is disposed on the top major surface of the semiconductor base through an insulation film 17. In a top major surface portion of the n− semiconductor layer 3 including a region which is immediately under the gate wire line GL, a p semiconductor layer 13 is selectively formed. The p semiconductor layer 13 is formed to maintain the breakdown voltage of the device 151 high. To achieve this object, the p semiconductor layer 13 is formed deeper than the p base layer 4.
In regions between the adjacent trenches 7 in the top major surface of the semiconductor base, an emitter electrode 11 is connected to both the p base layer 4 and the n+ emitter layer 5. An insulation layer 9 exists between the emitter electrode 11 and the gate electrode 10 and between the emitter electrode 11 and the gate wire line GL. The insulation layer 9 maintains electric insulation between these elements.
A collector electrode 12 is connected to a bottom major surface of the semiconductor base, that is, a surface of the p+ collector layer 1. The emitter electrode 11 and the collector electrode 12 serve as a pair of main electrodes.
In a condition where a positive collector voltage VCE is applied across the collector electrode 12 and the emitter electrode 11, when a positive gate voltage VGE exceeding a predetermined gate threshold voltage VGE(th) is applied across the gate electrode 10 and the emitter electrode 11, the channel region is reversed from the p type of the n type. As a result, electrons are injected into the n− semiconductor layer 3 from the emitter electrode 11 through the n+ emitter layer 5.
As the injected electrons forwardly bias across the p+ collector layer 1 and the n− semiconductor layer 3 (including the n+ buffer layer 2), holes are injected into the n− semiconductor layer 3 from the p+ collector layer 1. Since this greatly reduces the resistance of the n− semiconductor layer 3, a large collector current (which is a main current) flows from the collector electrode 12 to the emitter electrode 11.
Next, if the gate voltage VGE is returned to zero or a negative value, a channel region 6 returns to the p type. As this stops injection of electrons from the emitter electrode 11, injection of holes from the p+ collector layer 1 stops. Following this, electrons and holes staying within the n− semiconductor layer 3 (and the n+ buffer layer 2) are collected to the collector electrode 12 and the emitter electrode 11, or re-combined with each other and disappear.
By the way, as clearly shown in FIG. 29, a bipolar transistor which is formed by the n+ emitter layer 5, the p base layer 4, and the n− semiconductor layer 3 exists within an IGBT, in general, as a parasitic transistor. A hole current flowing in the p base layer 4 behaves as if it is a base current of the parasitic bipolar transistor. Hence, if the hole current flowing in the p base layer 4 exceeds a certain value, the parasitic bipolar transistor conducts (i.e., turns on).
Once the parasitic bipolar transistor conducts a parasitic thyristor which is formed by the n+ emitter layer 5, the p base layer 4, the n− semiconductor layer 3 and the p+ collector layer 1 also conducts. Conduction of the parasitic thyristor is called “latch-up”. Once the IGBT is latched up, the main current (i.e., collector current) flowing between the emitter electrode 11 from the collector electrode 12 keeps flowing, now independently of the gate voltage VGE. That is, it becomes impossible to control the collector current by means of the gate voltage VGE. This leads to destruction of the IGBT.
In the case of a trench IGBT, destruction due to latching up tends to occur at a particular portion of the semiconductor base, during a particular operation. For instance, when an induction load (hereinafter “L load”) is connected to the main electrodes and a large main current flows, latching up easily occurs. The extent of the ability of blocking a main current, which flows while the device is in an ON-state, when the device switches to an OFF-state is evaluated by a known RBSOA (Reverse Bias Safe Operation Area). Needless to mention, it is desirable that a large main current can be blocked, in other words, that the RBSOA is large.
FIG. 30 is a graph schematically showing changes in a collector current Ic and the collector voltage VCE during transition of the IGBT from the ON-state to the OFF-state with an L load connected. With the L load connected, when the collector current Ic decreases, inductive electromotive force which is expressed as {−L·dIc/dt} is generated across the L load where L denotes the force of induction of the L load.
A voltage which is equal to the sum of a d.c. power source voltage which is supplied from an external power source and this inductive electromotive force, is applied across the emitter electrode 11 and the collector electrode 12, as the collector voltage VCE. As a result, as shown in FIG. 30, during transition of the IGBT from the ON-state to the OFF-state, a surge voltage appears in the collector voltage VCE.
As shown in FIG. 30, when a power source voltage which is equivalent to a rated voltage of the IGBT is supplied and the value of the collector current Ic during the device ON-state corresponds to a rated current, the surge voltage excessively applies the collector voltage VCE, whereby an avalanche current is generated within the semiconductor base.
The avalanche current serves as a base current of the parasitic bipolar transistor described above. Hence, when the avalanche current which is equal to or larger than a certain value flows in the p base layer 4 in which the n+ emitter layer 5 exists, the parasitic bipolar transistor turns on, thereby destroying the IGBT. The avalanche current destroying the IGBT is developed in a portion of the semiconductor base with concentrated electric field, that is, a portion where electric field becomes strongest as a result of the application of the collector voltage VCE.
In general, electric field is concentrated at an extruded portion or a portion which is strongly warped. Hence, in general, electric field tends to concentrate around bottom portions of the trenches 7 or a side diffusion region which forms both end portions of the p semiconductor layer 13. However, in the device 151 which is shown in FIG. 29, the distance Wcel is set sufficiently small in order to sufficiently weaken electric field which is developed around the bottom portions of the trenches 7. Therefore, in the cell region CR, electric field is relatively weak. Further, since a guard ring 14 for weakening electric field is disposed around the p semiconductor layer 13, strong electric field is not developed in the side diffusion region of the p semiconductor layer 13 facing the guard ring 14.
Hence, in the device 151, electric field is strongest in the side diffusion region of the p semiconductor layer 13 facing the cell region CR. FIG. 31 is an expanded cross sectional view expanding a vicinity of such a side diffusion region. As shown in FIG. 31, in a region which is close to a boundary between the side diffusion region and the n− semiconductor layer 3, i.e., in a region where electric field is concentrated most strongly, an avalanche current is generated. In other words, pairs of holes H and electrons E are created.
Of these, the holes H flow into the emitter electrode 11 through the p base layer 4 which is in the vicinity of the p semiconductor layer 13, after passing through the n− semiconductor layer 3. At this stage, the flow of the holes H contributes as the base current of the parasitic bipolar transistor. Hence, when the avalanche current becomes large exceeding a certain limit, the parasitic bipolar transistor turns on. As a result, the device 151 is latched up, and is eventually destroyed.
As described above, in the conventional device 151, the avalanche current which is created in the side diffusion region of the p semiconductor layer 13 facing the cell region CR is a cause of latching up, and the RBSOA of the device is restricted by the avalanche current which is created in this side diffusion region.